The present invention is directed toward a processor for a computer, and more particularly, toward context switching and rescheduling of a processor.
A processor for a computer may execute a variety of contexts (programs) stored in a memory of the computer, where each program is made up of multiple instructions, and each of the instructions is stored at a specific location in the memory. The programs allow the processor to carry out various tasks, for example in a cellular telephone, outputting data to a display device, maintaining a radio link with a cellular base station or providing a calculator feature to the user of the cellular telephone. The processor executes a program by sequentially retrieving the instructions corresponding to the program from memory, and processing the instructions one at a time.
While processing instructions, the processor utilizes specific registers (i.e., accumulator registers, index registers) present in the processor by placing values in the specific registers and performing logical and arithmetic operations on the values, or otherwise manipulating the values. A program counter register indicates the memory location for the current instruction being processed by the processor and increments by the length in bytes of the just executed instruction so as to point to the next instruction to be processed.
Although various programs may reside in memory, not all programs have a need for processor resources at a given time, as they may have completed a task and are waiting for new input to process. Such a program is said to be in the xe2x80x9cinactive state.xe2x80x9d Other programs which have work to do are said to be in the xe2x80x9cactive state.xe2x80x9d Some active programs are said to be xe2x80x9csuspended in the active statexe2x80x9d where they have work to do but are suspended at a given instant due to the need to wait, for example, for completion of a slow I/O operation which they have invoked. The priority of an active, non-suspended program determines whether it is the program actually being executed at a given instant.
Commonly, each program is assigned a location in computer memory where a status bit in that memory location indicates whether the program is in the active state (presence of a xe2x80x9c1xe2x80x9d) or the inactive state (presence of an xe2x80x9c0xe2x80x9d). When a processor completes a program, or places a higher priority program into the active state, execution of a current program is stopped, and the program having the then highest priority active status is executed. To accomplish this, the processor must execute instructions to perform a xe2x80x9creschedule.xe2x80x9d Such a reschedule operation comprises software scanning, that is, successively testing the activity flags stored in the computer memory for each program in turn, in order of descending priority. The first xe2x80x9c1xe2x80x9d encountered indicates the active program with the highest priority and becomes the current program to be executed by the processor. However, the rescheduling operation consumes a significant number of microprocessor instructions to perform each program switch, reducing the efficiency of the processor. Further, as a significant number of instructions are required to perform a reschedule, a significant amount of battery power is consumed for each program switch.
The present invention is directed toward overcoming one or more of the problems discussed above.
In one aspect of the present invention, a system for switching resources of a computer among a plurality of programs is provided, including a processor for executing programs for the computer. The system further includes a set of register banks coupled to the processor for storing information for the plurality of programs, where each register bank includes a plurality of program information registers in correspondence with the plurality of programs, the set of register banks having a selection input for selecting a current program for the processor to execute. A status register is coupled to the processor for storing in a prioritized order a status bit corresponding to each program, where each status bit has a status bit address and indicates a status of the corresponding program as being one of active and inactive. A program determination logic circuit is coupled to the status register for determining the status bit address of a highest priority active program, and the program determination logic circuit is coupled to the set of register banks for providing the status bit address of the highest priority active program to the selection input, where the highest priority active program is selected as the current program.
In a preferred form, the program determination logic circuit of the system includes a network of multiple-input OR gates and two-way selector switches for determining the status bit address of the highest priority active program, a program address register coupled to the network for collecting the status bit address of the highest priority active program, the program address register being coupled to the selection input for providing the status bit address of the highest priority active program to the selection input.
In a preferred form, the system further includes set/reset logic coupled to the processor and the status register for changing the status of one of the plurality of programs by altering the status bit corresponding to the one program.
In a further preferred form, the system further includes a priority table coupled to the processor and the status register including a plurality of priority registers corresponding to the program information registers for storing a priority for the plurality of programs. A remapping table is coupled to the program determination logic circuit, the set of register banks, and the priority table, where the remapping table is the inverse of the priority table.
In another preferred form, an alternate priority table is coupled to the processor and the status register and comprises a plurality of alternate priority registers corresponding to the program information registers for storing the priority for the plurality of programs while the processor is executing the current program. An alternate remapping table is coupled to the program determination logic circuit, the set of register banks and the alternate priority table, where the alternate remapping table is the inverse of the alternate priority table. A selector is coupled to the priority table, the alternate priority table, the remapping table, the alternate remapping table, and the processor for selecting which of the priority table and the alternate priority table, and which of the remapping table and the alternate remapping table, are used for selecting which status bit address is sent to the selection input.
In another preferred form, the computer is a component in a mobile cellular telephone for controlling operation of the cellular telephone.
In another aspect, a method is provided for switching resources of a computer among a plurality of programs, the computer including a processor for executing programs, a set of register banks for storing a plurality of program information registers in correspondence with the plurality of programs and having a selection input for selecting a current program for the processor to execute, the method including storing in a prioritized order a status bit corresponding to each of the programs in a status register, each status bit having a status bit address and indicating a status of the corresponding program as being one of active and inactive, and communicating the status bits from the status register to a program determination logic circuit. At the program determination logic circuit, the status bit address of a highest priority status bit indicating active status is determined. The status bit address is communicated to the selection input of the set of register banks to select the current program.
In a preferred form, the step of determining the highest priority status bit includes determining if one of the status bits in a higher priority one-half of the status register indicates the active status, wherein if one of the status bits indicates the active status, the higher priority one-half of the status bits in the status register is selected and a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is recorded in a most significant location (MSL) in a program address register. If, however, none of the status bits indicate the active status, a lower priority one-half of the status bits in the status register are selected and the other of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is recorded in the MSL of the program address register. It is determined if one of the status bits in a higher priority one-half of the selected set of status bits indicates the active status, where if one of the selected status bits indicates the active status, the higher priority one-half of the selected status bits are selected, and xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is recorded in a next MSL in the program address register. If, however, none of the selected status bits indicate the active status, a lower priority one-half of the selected status bits are selected, and the other of a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is recorded in the next MSL in the program address register. The process repeats until the selected set of status bits contains two status bits, where the most significant bit (MSB) of the selected set of status bits is recorded as a least significant bit (LSB) in the program address register. If the status bit address xe2x80x9c0xe2x80x9d is designated as the highest priority, the values in the status bit address register are complemented after the LSB is recorded in the program address register to yield the status bit address of the highest priority active program.
In another preferred form, the computer is placed into a low power operation mode when none of the status bits indicate the active status.
In a further preferred form, the status of one of the plurality of programs is changed by altering the corresponding status bit. Altering the status bit includes determining the status bit address for the status bit corresponding to the one program, and placing a selected value in the determined status bit address. If a desired status for the one program is active, the selected value is a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. If, however, the desired status for the one program is inactive, the selected value is the other of a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
In a further preferred form, the prioritized order of the status bits may be altered. The computer further includes a priority table comprising a plurality of priority registers corresponding to the program information registers, wherein the step of altering the prioritized order of the status bits includes receiving a changed priority for one of the plurality of programs. A priority register address is determined for the priority register, the priority register address corresponding to the one program, and the changed priority is stored at the priority register address. The computer further includes a remapping table comprising a number of remapping registers corresponding to the priority registers, wherein a remapping table address for the remapping table is determined, the remapping table address corresponding to the changed priority, and a program address for the one program is stored at the remapping table address.
In another preferred form, the computer is used in a cellular telephone, and the step of communicating the status bit address to the selection input selects the current program for the processor of the cellular telephone to execute.